EEPROM and Flash memories (NOR and NAND) use a floating gate (FG) to store electrical charges to represent information. These memory devices suffer from degradation mechanisms after program/erase cycles that place limits on the number of erase/program operations a device can endure. Multi-Level Cell (MLC) Flash devices typically have significantly lower program/erase cycles endurance than Single-Level Cell (SLC) devices.
Various program and erase operations can lead to gain or loss of charge in neighboring cells, which is called a “disturb.” A disturb error occurs when the initial/programmed state of a cell changes as a result of programming or reading operations executed on nearby cells. Disturb errors are soft errors. A “read disturb” occurs when the amount of charge in a memory cell is altered by reading another cell, physically close to or sharing control lines with the disturbed cell. A single read disturb event may not produce enough change in charge content to effect an error, but cumulative read disturbs may eventually do so. The cumulative effect of read disturbs are reset by an erase operation. The specific matrix architecture of NAND Flash leads to more “read disturb” errors than NOR Flash. Program disturb errors result in a bit being set to the wrong value during page-programming. The bit error can happen on the page being programmed, but it can also occur on a different page in the block.
In U.S. Pat. No. 5,715,193 (Feb. 3, 1998), Robert Norman describes a method for monitoring the disturb effect on memory cell blocks in which each time an erase block is erased, the controller updates a table for the decode block which contains the erased block by adding a unit of disturb to the count for each other erase block in the decode block and resetting the count for the erased block to zero. Norman also states that preferably, the controller performs a refresh operation on each erase block whose disturb count reaches a predetermined maximum value. During the refresh operation, any necessary recovery procedures are performed to restore the proper charge to the floating gate of each cell of the erase block, thus preventing any erroneous reads of data that would otherwise occur (due to the disturb effect) absent performance of the refresh operation.
Multi-Level Cell (MLC) Flash devices can store multiple bits per memory cell by charging the floating gate of a transistor to different selected threshold voltage (VT) levels and, thereby, use the analog characteristic of the cell in mapping a bit pattern to a specific voltage level. In the case of NAND Flash, the VT of MLC devices are, conceptually, read by sequentially applying selected read voltage (VREAD) levels to the floating gates of the cells. Typically, the voltage ranges are selected with a guardband between each range to help ensure that the normal VT distributions do not overlap.
In NOR Flash, cells are connected in parallel to the bitlines, which allows cells to be individually read and programmed with all other transistors in series at known state. Thus, in NOR Flash, the transistors in series with the memory cell being queried are transistors associated with addressing functions only.
Published U.S. patent application 20080307270 by Tieniu Li (Dec. 11, 2008) describes a scheme implemented on a host device for detection of emerging bad blocks in a NAND memory that includes keeping at least a partial history of errors during read operations.
Published U.S. patent application 20100214847 by Nishihara, et al. describes a NAND Flash memory system that is said to reduce variations in the read disturb characteristic from chip to chip by that including a peripheral circuit that includes means for storing and retrieving a corrected read voltage for use by a memory controller. The memory controller performs data input/output control and data management on the Flash memory, adds error correction codes (ECC) upon writing, and analyzes the error correction codes upon reading.
Solid-state drives (SSDs) are data storage devices that are typically designed to be functional replacements for traditional hard disk drives (HDDs), but SSDs use solid-state memory to store data. The term SSD will be used herein only to refer to Flash memory based devices. SSDs generally use the same command interface as hard disk drives to allow SSDs to be used in place of HDDs in many applications without requiring software modifications. Hybrid devices that include both HDD and SSD features are also possible.
Given that degradation of memory content is progressive and unavoidable with time and number of program/erase cycles, there is a need to develop efficient error correcting codes that can take advantage of fundamental physics and operational details of Flash memory chips. These efficient error correcting codes need to make use of soft information retrievable at reading time without penalty to Flash memory readout performance. The present invention described below is related to inventions in other applications described in the Related Applications section above which will be generally referred to as Early Degradation Detection (EDD) systems for Flash memories. The present invention can stand alone or be complementary to EDD systems to further increase reliability and operational life of Flash memories.